MC68HC08AZ16 Datasheet, PDF (431/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Appendix A: Related Devices
1
1
1
1/2 AC367
Address bus
MC68HC08AZ0
D0
D1
D2
D3
A0 _D4
D5
A15 ^D6
D7
CS1
$1000 -
$FFFF
CS0
WSCLK
Program
Memory
1 WAIT-state
D0
D1
D2
$1000-
D3
$FFFF
D4
D5
(60K space)
D6
D7
CS
CS0 = $0000 - $0FFF
CS1 = $1000 - $FFFF, 1WS internal
Peripheral
7 WAIT-states
D7
D6
D5
D4
$0000-
$0FFF
D3
D2
(4K space
D1
less internal
addresses)
D0
CS
A0
A1
Figure 6. Defining WAIT states for EXIT addresses below $1000
In Figure 6, the user wants to maximize the address space allocated to
the program memory but requires to decode a slow external peripheral
with a 4byte address space. To avoid driving the data bus unnecessarily,
WSCLK is programmed to generate CS0+T4 which will only go low
MC68HC08AZ32
430
Appendix A: Related Devices
18-appA
MOTOROLA