MC68HC08AZ16 Datasheet, PDF(158/527 Page) Motorola, Inc – HCMOS Microcontroller Unit

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MC68HC08AZ16 Datasheet, PDF (158/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

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Low-Voltage Inhibit (LVI)

Functional description

Figure 1. LVI module block diagram

Table 1. LVI I/O register summary

Register Name

Bit 7 6

5

4

3

2

LVIStatusRegister(LVISR) LVIOUT

= Unimplemented

1 Bit 0 Addr.

$FE0F

Polled LVI

operation

Forced reset

operation

False reset

protection

In applications that can operate at VDD levels below the LVITRIPF level,

software can monitor VDD by polling the LVIOUT bit. In the mask option

register, the LVIPWRD and LVIRSTD bits must be at â0â to enable the

LVI module and to enable the LVI resets. Also, the LVIPRWD bit must

be at â0â to enable the LVI module, and the LVIRSTD bit must be at â1â to

disable LVI resets.

In applications that require VDD to remain above the LVITRIPF level,

enabling LVI resets allows the LVI module to reset the MCU when VDD

falls to the LVITRIPF level and remains at or below that level for 9 or more

consecutive CPU cycles. In the mask option register, the LVIPWRD and

LVIRSTD bits must be at â0â to enable the LVI module and to enable LVI

resets.

The VDD pin level is digitally filtered to reduce false resets due to power

supply noise. In order for the LVI module to reset the MCU,VDD must

remain at or below the LVITRIPF level for 9 or more consecutive CPU

cycles. VDD must be above LVITRIPR for only one CPU cycle to bring the

MCU out of reset.

3-lvi

MOTOROLA

Low-Voltage Inhibit (LVI)

MC68HC08AZ32

157

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