MC68HC08AZ16 Datasheet, PDF (154/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Computer Operating Properly Module (COP)
COP Control register (COPCTL)
COP Control register (COPCTL)
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Bit 7
6
5
4
3
2
1
Bit 0
COPCTL ^Read:
$FFFF _Write:
Low byte of reset vector
Clear COP counter
Reset:
Unaffected by reset
Figure 2. COP control register (COPCTL)
Interrupts
The COP does not generate CPU interrupt requests or DMA service
requests.
Monitor mode
The COP is disabled in monitor mode when V_DD + V_HI is present on the
IRQ1 pin or on the RST pin.
5-cop
MOTOROLA
Computer Operating Properly Module (COP)
MC68HC08AZ32
153