MC68HC08AZ16 Datasheet, PDF (269/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Timer Interface Module A (TIMA)
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic zero, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 7 shows, the CHxMAX bit takes effect in the cycle after it is set
or cleared. The output stays at the 100% duty cycle level until the
cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PTE/F/x/TACHx
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 7. CHxMAX Latency
TIMA channel
registers
(TACH0H/LÐTACHH
/L)
These read/write registers contain the captured TIMA counter value of
the input capture function or the output compare value of the output
compare function. The state of the TIMA channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIMA channel x registers (TACHxH) inhibits input captures until the low
byte (TACHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIMA channel x registers (TACHxH) inhibits output compares until
the low byte (TACHxL) is written.
Bit 7
6
TACH0H ^Read:
$0027 _Write:
Bit 15
14
Reset:
5
4
3
2
13
12
11
10
Indeterminate after reset
1
Bit 0
9
Bit 8
MC68HC08AZ32
268
Figure 8. TIMA channel registers (TACH0H/L–TACH3H/L)
Timer Interface Module A (TIMA)
24-tima
MOTOROLA