MC68HC08AZ16 Datasheet, PDF (127/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Mask Options
Functional description
MORA
$001F
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
SEC LVIRSTD LVIPWRD SSREC COPRS
Unaffected by reset
= Unimplemented
Figure 9. Mask option register A (MORA)
1
STOP
Bit 0
COPD
SEC — ROM security bit
SEC enables the ROM security feature. Setting the SEC bit prevents
dumping of the ROM contents.
1 = ROM security enabled
0 = ROM security disabled
LVIRSTD — LVI reset enable bit
LVIRSTD disables the reset signal from the LVI module. See
Low-Voltage Inhibit (LVI) on page 155.
1 = LVI module resets enabled
0 = LVI module resets disabled
LVIPWRD — LVI power enable bit
LVIPWRD disables the LVI module. See Low-Voltage Inhibit (LVI) on
page 155.
1 = LVI module power enabled
0 = LVI module power disabled
SSREC — Short stop recovery bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.
1 = STOP mode recovery after 32 CGMXCLK cycles
0 = STOP mode recovery after 4096 CGMXCLK cycles
If using an external crystal oscillator, the SSREC bit should not be set.
MC68HC08AZ32
126
Mask Options
2-morrom
MOTOROLA