MC68HC08AZ16 Datasheet, PDF (495/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Appendix C: ADC-15
I/O Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADICLK)
ADC Status and
Control Register
The following paragraphs describe the function of the ADC status and
control register.
Bit 7
6
5
4
3
2
1
Bit 0
ADSCR
$0038
Read: COCO
Write: R
AIEN
ADCO
CH4
CH3
CH2
CH1
CH0
Reset: 0
0
0
1
1
1
1
1
R = Reserved
Figure 2. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed. This bit is cleared whenever
the ADC status and control register is written or whenever the ADC
data register is read.
If the AIEN bit is a logic 1, the COCO is a read/write bit which selects
the CPU to service the ADC interrupt request. Reset clears this bit.
1 = conversion completed (AIEN = 0)
0 = conversion not completed (AIEN = 0)
or
CPU interrupt enabled (AIEN = 1)
MC68HC08AZ32
494
Appendix C: ADC-15
8-adc15
MOTOROLA