MC68HC08AZ16 Datasheet, PDF (132/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Break Module
Functional description
Table 1. Break I/O register summary
Register Name
Bit 7 6
5
4
3
2
BreakAddressRegisterHigh(BRKH) Bit15 14 13 12 11 10
BreakAddressRegisterLow(BRKL) Bit7 6
5
4
3
2
BreakStatus/ControlRegister(BRKSCR) BRKE BRKA
= Unimplemented
1 Bit 0 Addr.
9 Bit8 $FE0C
1 Bit0 $FE0D
$FE0E
IAB[15:8]
IAB[15:0]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
CONTROL
BKPT
(TO SIM)
IAB[7:0]
Flag protection
during break
interrupts
The system integration module (SIM) controls whether or not module
status bits can be cleared during the break state. The BCFE bit in the
SIM break flag control register (SBFCR) enables software to clear status
bits during the break state. See SIM break flag control register (SBFCR)
on page 93, and the Break Interrupts subsection for each module.
CPU during break
interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
3-brk
MOTOROLA
Break Module
MC68HC08AZ32
131