MC68HC08AZ16 Datasheet, PDF (228/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Serial Peripheral Interface Module (SPI)
Interrupts
Interrupts
Four SPI status flags can be enabled to generate CPU interrupt
requests:
Table 3. SPI interrupts
Flag
SPTE (Transmitter Empty)
SPRF (Receiver Full)
OVRF (Overflow)
MODF (Mode Fault)
Request
SPI Transmitter CPU Interrupt Request (DMAS = 0, SPTIE = 1)
SPI Receiver CPU Interrupt Request (DMAS = 0, SPRIE = 1)
SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1)
SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1, MODFEN = ’1’)
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests or transmitter DMA
service requests.
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt requests or receiver DMA service
requests, provided that the SPI is enabled (SPE = 1).
The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF flags to generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF flag is enabled to generate
receiver/error CPU interrupt requests.
19-spi
MOTOROLA
Serial Peripheral Interface Module (SPI)
MC68HC08AZ32
227