MC68HC08AZ16 Datasheet, PDF (112/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
CGM registers
PLLON — PLL on bit
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). See Base clock selector circuit on
page 105 Reset sets this bit so that the loop can stabilize as the MCU
is powering up.
1 = PLL on
0 = PLL off
BCS — Base clock select bit
This read/write bit selects either the crystal oscillator output,
CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM
output, CGMOUT. CGMOUT frequency is one-half the frequency of
the selected clock. BCS cannot be set while the PLLON bit is clear.
After toggling BCS, it may take up to three CGMXCLK and three
CGMVCLK cycles to complete the transition from one source clock to
the other. During the transition, CGMOUT is held in stasis. See Base
clock selector circuit on page 105 Reset and the STOP instruction
clear the BCS bit.
1 = CGMOUT driven by CGMVCLK/2
0 = CGMOUT driven by CGMXCLK/2
NOTE:
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. See Base clock selector circuit on page 105
PCTL[3:0] — Unimplemented bits
These bits provide no function and always read as ‘1’.
17-cgm
MOTOROLA
Clock Generator Module (CGM)
MC68HC08AZ32
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