MC68HC08AZ16 Datasheet, PDF (152/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Computer Operating Properly Module (COP)
Functional description
Table 1. COP I/O register summary
Register Name
Bit 7 6
5
4
3
2
COP Control Register (COPCTL)
1 Bit 0 Addr.
$FFFF
The COP counter is a free-running 6-bit counter preceded by a12-bit
prescaler. If not cleared by software, the COP counter overflows and
generates an asynchronous reset after 2¹³ – 2⁴ , or 2¹⁸ – 2⁴CGMXCLK
cycles, depending on the state of the COP rate select bit, COPRS in
MORA. When COPRS = 1, a 4.9152 MHz crystal, gives a COP timeout
period of 53.3ms. Writing any value to location $FFFF before overflow
occurs prevents a COP reset by clearing the COP counter and stages 5
through 12 of the prescaler.
NOTE:
In Expanded mode location $FFFF will be external to the MCU.
Therefore during the COP clearing operation, the peripheral located at
$FFFF will also be written to.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the SIM reset status register (SRSR). See SIM reset status
register (SRSR) on page 92.The COP should be cleared immediately
before entering or after exiting STOP mode to assure a full COP timeout
period. A CPU interrupt routine or a DMA service routine can be used to
clear the COP.
NOTE:
COP clearing instructions should be placed in the main program and not
in an interrupt subroutine. Such an interrupt subroutine could keep the
COP from generating a reset even while the main program is not working
properly.
3-cop
MOTOROLA
Computer Operating Properly Module (COP)
MC68HC08AZ32
151