MC68HC08AZ16 Datasheet, PDF (141/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Monitor ROM (MON)
Entering monitor
mode
Table 1 shows the pin conditions for entering monitor mode.
Table 1. Mode selection
Mode
V_DD + V_HI 1 0 1 1 Monitor
V_DD + V_HI 1 0 1 0 Monitor
CGMOUT
C-----G----M-----2X----C-----L---K--- _or C-----G----M-----2V----C-----L---K---
CGMXCLK
Bus
Frequency
C-----G----M---2--O-----U----T---
C-----G----M---2--O-----U----T---
Enter monitor mode by either
• Executing a software interrupt instruction (SWI) or
• Applying a ‘0’ and then a ‘1’ to the RST pin.
Once out of reset, the MCU waits for the host to send eight security bytes
(see Security on page 146). After the security bytes, the MCU sends a
break signal (10 consecutive ‘0’s) to the host computer, indicating that it
is ready to receive a command.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt.
The alternate vectors are in the $FE page instead of the $FF page and
allow code execution from the internal monitor firmware instead of user
code. The COP module is disabled in monitor mode as long as V_DD + V_HI
(^{see 5.0 Volt DC Electrical Characteristics on page 396), is applied to}
either the IRQ1 pin or the RST pin. See
System Integration Module (SIM) on page 71 for more information on
modes of operation.
NOTE:
Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The CGMOUT frequency is
equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
Table 2 is a summary of the differences between user mode and monitor
mode.
MC68HC08AZ32
140
Monitor ROM (MON)
4-mon
MOTOROLA