MC68HC08AZ16 Datasheet, PDF (164/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

External Interrupt Module (IRQ)
Functional description
Figure 3. IRQ module block diagram
Table 1. IRQ I/O register summary
Register Name
Bit 7 6
5
4
3
2
1
Bit 0 Addr.
IRQ Status/Control Register
(ISCR)
IRQF1 ACK1 IMASK1 MODE1 $001A
All of the external interrupt pins are falling-edge-triggered and are
software-configurable to be both falling-edge and low-level-triggered.
The MODE1 bit in the ISCR controls the triggering sensitivity of the IRQ1
pin.
When an interrupt pin is edge-triggered only, the interrupt latch remains
set until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt latch remains set until both of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to ’1’
The vector fetch or software clear may occur before or after the interrupt
pin returns to ’1’. As long as the pin is low, the interrupt request remains
pending. A reset will clear the latch and the MODEx1control bit, thereby
clearing the interrupt even if the pin stays low.
When set, the IMASK1 bit in the ISCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the corresponding IMASK bit is clear.
NOTE: The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. See Figure 4
3-irq
MOTOROLA
External Interrupt Module (IRQ)
MC68HC08AZ32
163