MC68HC08AZ16 Datasheet, PDF (204/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Serial Communications Interface Module (SCI)
I/O registers
NF — Receiver noise flag bit
This clearable, read-only bit is set when the SCI detects noise on the
PTE1/RxD pin. NF generates an NF CPU interrupt request if the NEIE
bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then
reading the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected
FE — Receiver framing error bit
This clearable, read-only bit is set when a logic is accepted as the
STOP bit. FE generates an SCI error CPU interrupt request if the
FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with
FE set and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
PE — Receiver parity error bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
SCI status register
2 (SCS2)
SCI status register 2 contains flags to signal the following conditions:
• Break character detected
• Incoming data
SCS2
$0017
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
0
0
0
0
0
0
= Unimplemented
Figure 10. SCI status register 2 (SCS2)
1
Bit 0
BKF
RPF
0
0
35-sci
MOTOROLA
Serial Communications Interface Module (SCI)
MC68HC08AZ32
203