MC68HC08AZ16 Datasheet, PDF (81/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

System Integration Module (SIM)
OSC1
PORRST
CGMXCLK
CGMOUT
RST
IAB
Computer
operating
properly (COP)
reset
4096
CYCLES
32
CYCLES
32
CYCLES
Figure 6. POR recovery
$FFFE
$FFFF
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, a value (any value) should be written
to location $FFFF. Writing to location $FFFF clears the COP counter and
bits 12 through 4 of the SIM counter. The SIM counter output, which
occurs at least every 2¹³ – 2⁴ CGMXCLK cycles, drives the COP
counter. The COP should be serviced as soon as possible out of reset
to guarantee the maximum amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ1/V_PP pin is held
at V_DD + V_HI while the MCU is in monitor mode. The COP module can be
disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ1/V_PP pin. This prevents the COP
from becoming disabled as a result of external noise. During a break
state, V_DD + V_HI on the RST pin disables the COP module.
MC68HC08AZ32
80
System Integration Module (SIM)
10-sim
MOTOROLA