MC68HC08AZ16 Datasheet, PDF (282/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Interrupts
Timer Interface Module B (TIMB)
Interrupts
The following TIMB sources can generate interrupt requests:
• TIMB overflow flag (TOF) — The TOF bit is set when the TIMB
counter value rolls over to $0000 after matching the value in the
TIMB counter modulo registers. The TIMB overflow interrupt
enable bit, TOIE, enables TIMB overflow CPU interrupt requests.
TOF and TOIE are in the TIMB status and control register.
• TIMB channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests
are enabled when CHxIE = 1. CHxF and CHxIE are in the TIMB
channel x status and control register.
Low-power modes
The WAIT instruction puts the MCU in low-power-consumption stibnite
mode.
WAIT mode
The TIMB remains active after the execution of a WAIT instruction. In
wait mode the TIMB registers are not accessible by the CPU. Any
enabled CPU interrupt request from the TIMB can bring the MCU out of
wait mode.
If TIMB functions are not required during wait mode, reduce power
consumption by stopping the TIMB before executing the WAIT
instruction.
11-timb
MOTOROLA
Timer Interface Module B (TIMB)
MC68HC08AZ32
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