MC68HC08AZ16 Datasheet, PDF (167/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

External Interrupt Module (IRQ)
IRQ module during break interrupts
The system integration module (SIM) controls whether the IRQ1
interrupt latch can be cleared during the break state. The BCFE bit in the
SIM break flag control register (SBFCR) enables software to clear the
latches during the break state. See SIM break flag control register
(SBFCR) on page 93.
To allow software to clear the IRQ1 latch during a break interrupt, a ’1’
is written to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latches during the break state, a ’0’ is written to the BCFE
bit. With BCFE at ’0’ (its default state), writing to the ACK1 bit in the IRQ
status and control register during the break state has no effect on the
IRQ latch.
IRQ status and control register (ISCR)
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. The ISCR performs the following functions:
• Indicates the state of the IRQ1 interrupt flag
• Clears the IRQ1 interrupt latch
• Masks IRQ1 interrupt requests
• Controls triggering sensitivity of the IRQ1 interrupt pin
Bit 7
6
5
4
3
2
1
Bit 0
ISCR
$001A
Read:
Write:
IRQF1
0
IMASK1 MODE1
ACK1
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 5. IRQ status and control register (ISCR)
MC68HC08AZ32
166
External Interrupt Module (IRQ)
6-irq
MOTOROLA