MC68HC08AZ16 Datasheet, PDF (340/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

I/O Ports
Port F
TBCH[1:0] — Timer B channel I/O bits
The PTF5/TBCH1-PTF4/TBCH0 pins are the TIMB input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTF5/TBCH1-PTF4/TBCH0
pins are timer channel I/O pins or general purpose I/O pins. See TIMB
status and control register (TBSC) on page 284.
NOTE:
Data direction register F(DDRF) does not affect the data direction of port
F pins that are being used by TIMA and TIMB. However, the DDRF bits
always determine whether reading port F returns the states of the
latches or the states of the pins. See Table 7.
Data direction
register F (DDRF)
Data direction register F determines whether each port F pin is an input
or an output. Writing a logic one to a DDRF bit enables the output buffer
for the corresponding port F pin; a logic zero disables the output buffer.
DDRF
$000D
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
0
DDRF6 DDRF5 DDRF4 DDRF3 DDRF2
0
0
0
0
0
= Unimplemented
Figure 17. Data direction register F (DDRF)
1
DDRF1
0
Bit 0
DDRF0
0
DDRF[6:0] — Data direction register F bits
These read/write bits control port F data direction. Reset clears
DDRF[6:0], configuring all port F pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
NOTE: Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
19-io
MOTOROLA
I/O Ports
MC68HC08AZ32
339