MC68HC08AZ16 Datasheet, PDF (336/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

I/O Ports
Port E
MISO — Master In/Slave Out
The PTE5/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTE5/MISO pin is available for general-purpose
I/O. See SPI control register (SPCR) on page 237.
SS — Slave Select
The PTE4/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set, the
PTE4/SS pin is available for general-purpose I/O. See SPI control
register (SPCR) on page 237. When the SPI is enabled as a slave,
the DDRF0 bit in data direction register E (DDRE) has no effect on the
PTE4/SS pin.
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SPI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. See Table 6.
TACH[1:0] — Timer A channel I/O bits
The PTE3/TACH1–PTE2/TACH0 pins are the TIMA input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0
pins are timer channel I/O pins or general-purpose I/O pins. See TIMA
channel status and control registers (TASC0–TASC3) on page 264.
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the TIMA. However, the DDRE bits
always determine whether reading port E returns the states of the
latches or the states of the pins. See Table 6.
RxD — SCI Receive data input
The PTE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and
the PTE1/RxD pin is available for general-purpose I/O. See SCI
control register 1 (SCC1) on page 190.
15-io
MOTOROLA
I/O Ports
MC68HC08AZ32
335