MC68HC08AZ16 Datasheet, PDF (76/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

System Integration Module (SIM)
SIM bus clock control and generation
SIM bus clock control and generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 2. This clock can come
from either an external oscillator or from the on-chip PLL. See
Clock Generator Module (CGM) on page 95.
OSC1
CLOCK
SELECT
÷2
CGMVCLK
CIRCUIT
PLL
BCS
PTC3
MONITOR MODE
USER MODE
CGM
CGMXCLK
A
CGMOUT
B _S*
*When S = 1,
CGMOUT = B
Figure 2. CGM clock signals
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
Bus timing
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. See Clock Generator Module (CGM) on page 95.
Clock start-up
from POR or LVI
reset
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has been completed. The RST pin is driven low by the SIM
during this entire period. The IBUS clocks start upon completion of the
timeout.
5-sim
MOTOROLA
System Integration Module (SIM)
MC68HC08AZ32
75