MC68HC08AZ16 Datasheet, PDF (284/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Timer Interface Module B (TIMB)
I/O Signals
I/O Signals
Port F Shares two of its pins with the TIMB and Port D shares one.
PTD4/TBCLK is an external clock input to the TIMB prescaler. The two
TIMB channel I/O pins are PTF4/TBCH0 and PTF5/TBCH1.
TIMB clock Pin
(PTD4/TBLCK)
PTD4/TBCLK is an external clock input that can be the clock source for
the TIMB counter instead of the prescaled internal bus clock. Select the
PTD4/TBCLK input by writing logic ones to the three prescaler select
bits, PS[2:0]. See TIMB status and control register (TBSC) on page 284.
The minimum TBCLK pulse width, TBCLK_LMIN or TBCLK_HMIN, is:
1
bus frequency
+ t_SU
The maximum TCLK frequency is:
bus frequency ÷ 2
is available as a general-purpose I/O pin when not used as the TIMB
clock input. When the PTD4/TBCLK pin is the TIMB clock input, it is an
input regardless of the state of the DDR5 bit in data direction register D.
TIMB channel I/O
pins
(PTF5/TBCH1ÐPTF4/
TBCH0)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTF5/TBCH1 and PTF4/TBCH0
can be configured as buffered output compare or buffered PWM pins.
TBCH0 has an additional source for the input capture signal i.e
CANTIMCAP. See Figure 1.
This signal is generated by the msCAN08 which generates a timer signal
whenever a valid frame has been received or transmitted. The signal is
routed into TBCH0 under the control of the Timer Link Enable (TLNKEN)
bit in the CMCR0 see 23.12.2 msCAN08 module control register
(CMCR0).
13-timb
MOTOROLA
Timer Interface Module B (TIMB)
MC68HC08AZ32
283