MC68HC08AZ16 Datasheet, PDF (515/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Index
FE bit (SCI framing error bit) . . . . . . . . . . .185
FE bit (SCI receiver framing error bit) . . . .203
FEIE bit (SCI framing error interrupt enable
bit). . . . . . . . . . . . . . . . . . . . . . . . . .185
FEIE bit (SCI receiver framing error interrupt
enable bit). . . . . . . . . . . . . . . . . . . .198
flag protection in break mode . . . . . . . . . . .87
f_NOM (nominal center-of-range frequency) .100
f_rclk (PLL reference clock frequency) . . . . .103
f_RCLK (PLL reference clock frequency) . . . .100
f_RDV (PLL final reference frequency) . . . . .100
functional operating range. . . . . . . . . . . . .395
f_VCLK (VCO output frequency) . . . . . . . . . .100
f_VRS (VCO programmed center-of-range fre-
quency). . . . . . . . . . . . . .100, 104, 115
input capture . . . . . . .250, 275, 292, 458, 461
interrupt
external interrupt pin (IRQ1) . . . . . . . . . 17
interrupt status and control register (ISCR) . .
162
interrupts
ADC . . . . . . . . . . . . . . . . . . . . . . . 305, 491
CGM . . . . . . . . . . . . . . . . . . . . . . . . . . 116
msCAN08 . . . . . . . . . . . . . . . . . . . . . . 360
IRQ status and control register (ISCR) . . . 166
IRQ1 latch . . . . . . . . . . . . . . . . . . . . . . . . . 162
IRQ1/V_PP pin . . . . . . . . . . . . 17, 153, 161, 165
triggering sensitivity . . . . . . . . . . . . . . . 163
IRQ2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . 161
IRST signal . . . . . . . . . . . . . . . . . . . . . . . . . 77
H
H bit
CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
I
I bit
CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
I bit (interrupt mask) . . . . . . . . . . . . .163, 167
I/O port register summary . . . . . . . . . . . . .322
I/O registers
locations. . . . . . . . . . . . . . . . . . . . . . . . .26
IAB (internal address bus). . . . . . . . . . . . .130
IBUS . . . . . . . . . . . . . . . . . . . . . . . . . . .75, 82
IDLE bit (SCI receiver idle bit) . . . . . .184, 200
idle character. . . . . . . . . . . . . . . . . . . . . . .177
ILAD
SRSR . . . . . . . . . . . . . . . . . . . . . . . . . . .93
ILIE bit (SCI idle line interrupt enable bit) 184,
195
ILOP
SRSR . . . . . . . . . . . . . . . . . . . . . . . . . . .93
ILOP bit (illegal opcode reset bit) . . . . . . . .93
ILTY bit (SCI idle line type bit). . . . . . . . . .192
IMASK1 bit (IRQ1 interrupt mask bit) 163, 167
IMASKK
Keyboard interrupt mask bit . . . . . . . . .319
index register (H:X) . . . . . . . . . . . . . . . .56, 86
K
KB
I/O register summary . . . . . . . . . . . . . . 315
KBIE4-KBIE0
Keyboard interrupt enable bits. . . . . . . 319
keyboard interrupt control register (KBICR) . .
318
Keyboard interrupt enable register (KBIER) . .
319
KEYF
Keyboard flag bit . . . . . . . . . . . . . . . . . 318
L
L (VCO linear range multiplier) . . . . . . . . . 104
literature distribution centers. . . . . . . . . . . 521
LOCK
PBWC . . . . . . . . . . . . . . . . . . . . . . . . . 112
LOOPS bit (SCI loop mode select bit) . . . 191
LVI
SRSR. . . . . . . . . . . . . . . . . . . . . . . . . . . 93
LVI module . . . . . . . . . . . . . . . . . . . . . . . . 159
LVI status register (LVISR) . . . . . . . . 156, 158
LVI trip voltage . . . . . . . . . . . . . . . . . . . . . 155
LVIOUT bit (LVI output bit) . . . . . . . . 156, 158
LVIPWR
MORA . . . . . . . . . . . . . . . . . . . . . . . . . 126
LVIPWR bit (LVI power enable bit) . . . . . . 159
MC68HC08AZ32
514
Index
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