82374EB Datasheet, PDF (98/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
4 0 ADDRESS DECODING
The ESC contains an address decoder to decode EISA ISA master cycles The ESC address decoder uses
the address line LA 31 2 and byte enable BE 3 0 to decode EISA master cycles For ISA master cycles
the ESC uses address line LA 31 2 SA 1 0 and high byte enable SHBE for address decode
The ESC decodes the following set of addresses
1 BIOS memory space
2 I O addresses contained within the ESC
3 Configuration registers
4 X-Bus Peripherals
5 Memory addresses for accessing APIC
4 1 BIOS Memory Space
The ESC supports a total of 512 KBytes of BIOS The ESC will assert the LBIOSCS signal for memory cycles
decoded to be in the BIOS space The 512 KBytes of BIOS includes the conventional 128 KBytes of BIOS and
384 KBytes of enlarged BIOS
The 128 KBytes conventional BIOS memory space is mapped at 1 MByte boundary between memory address
000E0000h–000FFFFFh The 128 KByte conventional BIOS memory space is split into one 64 KByte region
and four 16 KByte regions These regions are Low BIOS region 1 (000E0000h – 000E3FFFh) Low BIOS region
2 (000E4000h–000E7FFFh) Low BIOS region 3 (000E8000h – 000EBFFFh) and Low BIOS region 4
(000EC000h–000EFFFFh) and High BIOS region (000F0000h – 000FFFFFh) The ESC will assert the
LBIOSCS signal for memory cycles to these regions if the corresponding configuration bits in the BIOS Chip
Select A register are set to enable (see Table 3)
The conventional BIOS is aliased at multiple memory regions The aliased memory regions are at 16 MByte
boundary (High BIOS only) 4 GByte minus 1 MByte boundary and 4 GByte boundary The ESC will assert
LBIOSCS for memory cycles to these aliased regions if the corresponding configuration bits in the BIOS
Chip Select B register are also set to enable (see Table 3)
The ESC supported VGA BIOS on the motherboard by aliasing the VGA BIOS region to the conventional BIOS
region The VGA BIOS is accessed at memory region 0000C0000h – 0000C7FFF The VGA BIOS region is
divided into a Low VGA region (000C0000h–000C3FFFh) and a High VGA region (000C4000h – 000C7FFFh)
If the BIOS Chip Select B register bit 0 (Low VGA BIOS Enable) and bit 1 (High VGA BIOS Enable) are set to
enable memory accesses to Low VGA BIOS region and High VGA BIOS region will be aliased to conventional
Low BIOS region 1 and Low BIOS region 2 respectively and the ESC will assert LBIOSCS
The ESC supports the 384 KBytes of enlarged BIOS as specified by the PCI specification This 384 KByte
region is mapped in memory space below the 4 GByte aliased conventional BIOS The enlarged BIOS is
accessed between FFF80000h–FFFDFFFFh memory space If the enlarged BIOS is enabled in the BIOS
Enable Chip Select 1 register bit 5 (Enlarged BIOS Enable) the ESC will assert LBIOSCS signal for access-
es to this region
BIOS Location Auto-Detection
Some applications require that Flash-EPROM based BIOS be updated in the system from the data coming
from the floppy disk To support this the X-bus signals must be properly controlled (i e the ESC’s X-Bus
control logic must be aware of physical BIOS location X-bus or ISA Bus) This is supported transparently to
the software by configuring ESC’s X-Bus logic during RESET using the SLOWH pin
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