82374EB Datasheet, PDF (88/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Bit
Description
7 System Board Error RO Bit 7 is set if the PERR line is pulsed This interrupt is enabled by setting
bit 2 to 0 To reset the interrupt set bit 2 to 0 and then set it to 1 Note that this bit does not reflect
status of an NMI caused by SERR which is enabled and disabled cleared via the MS Register
6 IOCHK NMI Source RO Bit 6 is set if an expansion board asserts IOCHK on the ISA EISA Bus
This interrupt is enabled by setting bit 3 to 0 To reset the interrupt set bit 3 to 0 and then set it to 1
5 Timer 1 Counter 2 RO The Timer 1 Counter 2 OUT signal state is reflected in bit 5 The value on
this bit following a read is the current state of the Counter 2 OUT signal Counter 2 must be
programmed following a reset for this bit to have a determinate value
4 Refresh Cycle Toggle RO The Refresh Cycle Toggle signal toggles from either 0 to 1 or 1 to 0
following every refresh cycle
3 IOCHK NMI Enable R W When bit 3 is a 1 IOCHK NMI’s are disabled and cleared and when
bit 3 is a 0 (default) IOCHK NMI’s are enabled
2 PCI System Board Error R W When bit 2 is a 1 the system board error is disabled and cleared
When bit 2 is a 0 (default) the system board parity error is enabled Note that NMI generation for
system board errors is enabled disabled via bit 3 (System Error) of the Mode Select Register
Following reset bit 2 is a 0 and system board errors are enabled
1 Speaker Data Enable R W Speaker Data Enable is ANDed with the Timer 1 Counter 2 OUT signal
to drive the SPKR output signal When bit 1 is a 0 (default) the result of the AND is always 0 and the
SPKR output is always 0 When bit 1 is a 1 the SPKR output is equivalent to the Counter 2 OUT signal
value
0 Timer 1 Counter 2 Gate Enable R W When bit 0 is a 0 Timer 1 Counter 2 counting is disabled
Counting is enabled when bit 0 is a 1 This bit controls the GATE input to Counter 2
3 4 11 NMIERTC NMI CONTROL AND REAL-TIME CLOCK ADDRESS
Register Location
Default Value
Attribute
Size
070h
See below
Write Only
8 Bits
The most-significant bit enables or disables all NMI sources including PERR SERR IOCHK Fail-Safe
Timer Bus Timeout and the NMI Port Write an 80h to The NMIERTC Register to mask the NMI signal This
register is shared with the real-time clock The real-time-clock uses the lower six bits of this port to address
memory locations Writing to port 70h sets both the enable disable bit and the memory address pointer Do
not modify the contents of this register without considering the effects on the state of the other bits
Bit
Description
7 NMI Enable Setting bit 7 to a 1 will disable all NMI sources Setting the bit to a 0 enables the NMI
interrupt
6 0 Real-Time Clock Address Used by the Real-Time Clock on the Base I O component to address
memory locations Not used for NMI enabling disabling
88