82374EB Datasheet, PDF (43/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Pin Name
Description
32
Serial Port B Address Decode If either COM1 or COM2 address ranges are selected these
bits default to disabled upon PCIRST
Bits 3 2
00
01
10
11
Decode
3F8h–3FFh (COM1)
2F8h–2FFh (COM2)
Reserved
Port A disabled
10
Serial Port A Address Decode If either COM1 or COM2 address ranges are selected these
bits default to disabled upon PCIRST
Bits 1 0
00
01
10
11
Decode
3F8h–3FFh (COM1)
2F8h–2FFh (COM2)
Reserved
Port A disabled
3 1 9 EISAID 4 1 EISA ID REGISTERS
Address Offset
Default Value
Attribute
Size
50h 51h 52h 53h
00h 00h 00h 00h
Read Write
8 Bits each
These 8 bit registers contain the EISA motherboard ID The data in the register is reflected on the data bus for
I O cycles addressed to 0C80h–0C83h respectively
Bit
Description
7 0 EISA ID Byte These bits contain the EISA Motherboard ID information On power up these bits
default to 00h These bit are written with the ID value during configuration The value of these bits are
reflected in I O registers 0C80h–0C83h
3 1 10 SGRBA SCATTER GATHER RELOCATE BASE ADDRESS REGISTER
Address Offset
Default Value
Attribute
Size
57h
04h
Read Write
8 Bits
The value programmed in this register determines the high order I O address of the S-G registers The default
value is 04h
Bit
Description
7 0 S-G Relocate Byte These bits determine the I O location of the Scatter Gather Registers The
Scatter-Gather register relocation range is xx10h – xx3Fh (default 0410h – 043Fh) These bits
determine the Byte 1 of the I O address Address signals LA 15 8 are compared against the contents
of this register (bit 7 0 ) to determine I O accesses to the Scatter-Gather registers The default on
Power up is 04h
43