82374EB Datasheet, PDF (19/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Pin Name
LA 31 27
CPG 4 0
LA 26 24
and
LA 23 2
BE 3 0
M IO
WR
Type
Description
t s EISA ADDRESS BUS CONFIGURATION RAM PAGE ADDRESS These are
multiplexed signals These signals behave as the EISA address bus under all
conditions except during access cycle to the Configuration RAM
EISA Address Bus LA 31 27 are directly connected to the EISA address bus
The ESC uses the address bus in conjunction with the BE 3 0 signals as inputs to
decode accesses to its internal resources except in DMA and Refresh modes
During DMA and Refresh modes these are outputs and the ESC uses these signals
in conjunction with BE 3 0 to drive Memory address
Configuration Ram Page Address CPG 4 0 are connected to Configuration SRAM
address lines During I O access to 0800h-08FFh the ESC drives these signals with
the configuration page address (the value contained in register 0C00h) The
Configuration RAM Page Address function can be disabled by setting Mode Select
register bit 5 ^e 0
t s EISA ADDRESS BUS These signals are directly connected to the EISA address
bus The ESC uses the address bus in conjunction with the BE 3 0 signals as
inputs to decode accesses to its internal resources except in DMA and Refresh
modes During DMA and Refresh modes these are outputs and the ESC uses
these signals in conjunction with BE 3 0 to drive Memory address
t s BYTE ENABLES BE 3 0 signals are directly connected to the EISA address bus
These signals indicate which byte on the 32-bit EISA data bus are involved in the
current cycle BE 3 0 are inputs during EISA master cycles which do not require
assembly disassembly operation For EISA master assembly disassembly cycles
ISA master cycles DMA and Refresh cycles BE 3 0 are outputs
BE0 Corresponds to byte lane 0-SD 7 0
BE1 Corresponds to byte lane 0-SD 15 8
BE2 Corresponds to byte lane 0-SD 23 16
BE3 Corresponds to byte lane 0-SD 31 24
t s MEMORY OR I O CYCLE M IO signal is used to differentiate between memory
cycles and I O cycles on the EISA bus A High value on this signal indicates a
memory cycle and a Low value indicates an I O cycle M IO is an input to the
ESC during EISA master cycles and M IO is an output during ISA DMA and ESC
initiated Refresh cycles M IO is floated during ISA master initiated Refresh
cycles
t s WRITE OR READ CYCLE W R signal is used to differentiate between write and
read cycles on the EISA bus A High value on this signal indicates a Write cycle and
a Low value indicates a Read cycle W R is an input to the ESC during EISA
master cycles and W R is an output during ISA DMA and Refresh cycles
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