82374EB Datasheet, PDF (9/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

CONTENTS
7 2 2 EISA MASTER PREEMPTION
7 2 3 DMA PREEMPTION
7 3 Slave Timeouts
7 4 Arbitration During Non-Maskable Interrupts
8 0 INTERVAL TIMERS
8 1 Interval Timer Address Map
8 2 Programming The Interval Timer
9 0 INTERRUPT CONTROLLER
9 1 Interrupt Controller Internal Registers
9 2 Interrupt Sequence
9 3 80x86 Mode
9 3 1 ESC INTERRUPT ACKNOWLEDGE CYCLE
9 4 Programming The Interrupt Controller
9 5 End-Of-Interrupt Operation
9 5 1 END OF INTERRUPT (EOI)
9 5 2 AUTOMATIC END OF INTERRUPT (AEOI) MODE
9 6 Modes Of Operation
9 6 1 FULLY NESTED MODE
9 6 2 THE SPECIAL FULLY NESTED MODE
9 6 3 AUTOMATIC ROTATION (EQUAL PRIORITY DEVICES)
9 6 4 SPECIFIC ROTATION (SPECIFIC PRIORITY)
9 6 5 POLL COMMAND
9 6 6 CASCADE MODE
9 6 7 EDGE AND LEVEL TRIGGERED MODES
9 7 Register Functionality
9 7 1 INITIALIZATION COMMAND WORDS
9 7 2 OPERATION CONTROL WORDS (OCWS)
9 8 Interrupt Masks
9 8 1 MASKING ON AN INDIVIDUAL INTERRUPT REQUEST BASIS
9 8 2 SPECIAL MASK MODE
9 9 Reading The Interrupt Controller Status
9 10 Non-Maskable Interrupt (NMI)
10 0 ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
10 1 Physical Characteristics Of APIC Bus
10 2 Arbitration For APIC Bus
10 3 Bus Message Formats
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