82374EB Datasheet, PDF (84/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
3 4 6 OCW1 OPERATION CONTROL WORD 1
Register Location
Default Value
Attribute
Size
021h INT CNTRL-1
0A1h INT CNTRL-2
xxh
Read Write
8 Bits
OCW1 sets and clears the mask bits in the interrupt Mask register (IMR) Each interrupt request line may be
selectively masked or unmasked any time after initialization A single byte is written to this register Each bit
position in the byte represents the same-numbered channel Bit 0^eIRQ 0 bit 1^eIRQ 1 and so on Setting
the bit to a 1 sets the mask and clearing the bit to a 0 clears the mask Note that masking IRQ 2 on CNTRL-1
will also mask all of controller 2’s interrupt requests (IRQ8-IRQ15) Reading OCW1 returns the controller’s
mask register status
The IMR stores the bits which mask the interrupt lines to be masked The IMR operates on the IRR Masking
of a higher priority input will not effect the interrupt request lines of lower priority
Unlike status reads of the ISR and IRR for reading the IMR no OCW3 is needed The output data bus will
contain the IMR whenever I O read is active and the I O port address is 021h or 0A1h (OCW1)
All writes to OCW1 must occur following the ICW1-ICW4 initialization sequence since the same I O ports are
used for OCW1 ICW2 ICW3 and ICW4
Bit
Description
7 0 Interrupt Request Mask When a 1 is written to any bit in this register the corresponding IRQ x line
is masked For example if bit 4 is set to a 1 then IRQ 4 will be masked Interrupt requests on IRQ 4
will not set Channel 4’s interrupt request register (IRR) bit as long as the channel is masked
When a 0 is written to any bit in this register the corresponding IRQ x mask bit is cleared and
interrupt requests will again be accepted by the controller
Note that masking IRQ 2 on CNTRL-1 will also mask the interrupt requests from CNTRL-2 which is
physically cascaded to IRQ 2
3 4 7 OCW2 OPERATION CONTROL WORD 2
Register Location
Default Value
Attribute
Size
020h INT CNTRL-1
0A0h INT CNTRL-2
xxh
Write Only
8 Bits
OCW2 controls both the Rotate Mode and the End of Interrupt Mode and combinations of the two The three
high order bits in an OCW2 write represent the encoded command The three low order bits are used to select
individual interrupt channels during three of the seven commands The three low order bits (labeled L2 L1 and
L0) are used when bit 6 the SL bit is set to a 1 during the command
Following a reset and ICW initialization the controller enters the fully nested mode of operation Non-specific
EOI without rotation is the default Both rotation mode and specific EOI mode are disabled following initializa-
tion
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