82374EB Datasheet, PDF (47/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
3 1 17 PAC PCI APIC CONTROL REGISTER
Address Offset
Default Value
Attribute
Size
70h
00h
Read Write
8 Bits
The PAC Register controls the operation of the INTR signal in APIC PIC configuration and the routing of the
System Management Interrupt (SMI)
Bit
Description
7 2 Reserved
1 SMI Routing Control (SMIRC) When SMIRC^e1 the SMI is routed via the APIC When SMIRC^e0
the SMI is routed via the SMI signal Note that when SMRC^e1 INTR can not be routed through the
APIC since it is sharing the APIC interrupt input with SMI
0 INTR Routing Control (INTRC) When APIC is enabled (in mixed or pure APIC mode) this bit allows
the ESC’s external INTR signal to be masked (forces INTR to the inactive state but does not tri-states
the signal) Thus the CPU’s INTR pin can be used (by providing a simple -gate) for the APIC Local
Interrupt (LINTRx) However INTR must not be masked via this bit when APIC is disabled and INTR is
the only mechanism to signal the 8259 recognized interrupts to the CPU When INTRC^e1 INTR is
disabled (APIC must be enabled) When INTRC^e0 INTR is enabled
3 1 18 TESTC TEST CONTROL REGISTER
Address Offset
Default Value
Attribute
Size
88h
00h
Read Write
8 Bits
This register provides control for ESC manufacturing test modes The functionality of this register is reserved
3 1 19 SMICNTL SMI CONTROL REGISTER
Address Offset
Default Value
Attribute
Size
A0h
08h
Read Write
8 Bits
For the 82374SB the SMICNTL Register provides Fast Off Timer control STPCLK enable disable and CPU
clock scaling This register also enables disables the system management interrupt (SMI)
Bit
Description
7 Reserved Must be 0 when writing this register
6 4 Reserved
3 Fast Off Timer Freeze (CTMRFRZ) This field enables disables the Fast Off Timer When this bit is 1
the Fast Off timer stops counting This prevents time-outs from occurring while executing SMM code
When this bit is 0 the Fast Off timer counts
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