82374EB Datasheet, PDF (32/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Pin Name
RTCWR
PIRQ2
Type
Description
out REAL TIME CLOCK WRITE COMMAND PCI INTERRUPT REQUEST 2 This signal
pin has two functions and the function is selected via the Mode Select Register
When functioning as RTCWR this signal is asserted for I O writes to address
0071h If the Power On Password protection is enabled (I O Port 92h bit 3^e1) then
for accesses to RTC addresses 36h – 3Fh (Port 70h) RTCWR will not be generated
For details on PIRQ2 see the Mode Select Register description For the PIRQ2
function an external pull-up resistor (10K – 20K) must be added to this signal
2 11 6 FLOPPY DISK CONTROLLER INTERFACE
Pin Name
FDCCS
PIRQ1
DSKCHG
Type
out
in
Description
FLOPPY DISK CONTROLLER CHIP SELECT PCI INTERRUPT REQUEST 1 This
signal has two functions and the function is selected via the Mode Select Register As
FDCCS is asserted for I O cycles to the floppy drive controller When functioning as
FDCCS this signal is also asserted when IDECS1 is decoded See the Mode
Select Register description for details on the PIRQ1 function of this signal Note that
for the PIRQ1 function an external pull-up resistor (10 KX –20 KX) must be added to
this signal
DISK CHANGE DSKCHG signal is tied directly to the DSKCHG signal of the floppy
controller This signal is inverted and driven onto system data line 7 (SD7) during I O
read cycles to floppy address locations 3F7h (primary) or 377h (secondary) as
indicated by the table below Note that the primary and secondary locations are
programmed in the X-Bus Address Decode Enable Disable Register ‘‘A’’
FDCCS IDECSx State of SD7
Decode Decode (output)
State of
XBUSOE
Enabled
Enabled
Disabled
Disabled
Enabled
Disabled
Enabled
Disabled
Tri-stated
Driven
via DSKCHG
Tri-stated
Tri-stated
Enabled
Disabled
Disabled (note)
Disabled
NOTE
This mode is not supported because of potential contention between the X-Bus
buffer and a floppy on the ISA bus driving the system bus at the same time
during shared I O accesses
This signal is also used to determine if the floppy controller is present on the X-Bus It
is sampled on the trailing edge of RESET and If high the Floppy is present For
systems that do not support a Floppy via the ESC this pin should strapped low If
sampled low the SD7 function and XBUSOE will not be enable for accesses to the
floppy disk controller
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