82374EB Datasheet, PDF (63/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
3 2 10 DMA BASE AND CURRENT HIGH BYTE WORD COUNT REGISTER DMA BASE HIGH BYTE
WORD COUNT REGISTER
Register Location
Default Value
Attribute
Size
401h DMA Channel 0
403h DMA Channel 1
405h DMA Channel 2
407h DMA Channel 3
4C6h DMA Channel 5
4CAh DMA Channel 6
4CEh DMA Channel 7
00h
Read Write
8 Bits per channel
Each channel has a 8-bit Current High Byte Word Count register This register provides the uppermost 8 bits
for the number of transfers to be performed The byte word count is decremented after each transfer The
intermediate value of the byte word count is stored in the register during the transfer When the value in the
register goes from zero to FFFFh a TC may be generated
Following the end of a DMA service it may also be re-initialized by an autoinitialization back to its original value
autoinitialize can occur only when a TC occurs If it is not autoinitialized this register will have a count of
FFFFh after TC
The High Byte Word Count register must be the last Byte Word Count register programmed Writing to the
8237 Compatible Byte Word Count registers will clear the High Byte Word Count register to 00h
When the Extended Mode register is programmed for ‘‘count by word’’ transfers to from a 16-bit I O with
shifted address the Byte Word count will indicate the number of 16-bit words to be transferred
When the Extended Mode register is programmed for ‘‘count by byte’’ transfers the Byte Word Count will
indicate the number of bytes to be transferred The number of bytes does not need to be a multiple of the
transfer size in this case
Each channel has a Base High Byte Word Count register located at the same port address as the correspond-
ing Current High Byte Word Count register These registers store the original value of their associated Current
registers During autoinitialize these values are used to restore the Current registers to their original values
Normally the Base registers are written simultaneously with their corresponding Current register in successive
8 bit bytes by the microprocessor However in Chaining Mode only the Base register set is programmed and
the Current register is not effected The Base registers cannot be read by any external agents
In Scatter-Gather mode these registers store the lowest 8 bits of the current High Byte Word Count During a
Scatter-Gather transfer the DMA will load a reserve buffer into the base High Byte Word Count register
In Chaining Mode these register store the lowest 8 bits of the current High Byte Word Count The CPU will
then program the base register set with a reserve buffer
Bit
Description
7 0 Base and Current High Byte Word Count These bits represent the 8 high order byte word count
bits used when counting down a DMA transfer Upon reset or Master Clear the value of these bits is
00h
63