82374EB Datasheet, PDF (139/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
After reset is negated all channels will be set to Address Compatibility Mode The DMA Master Clear com-
mand will also reset the proper channels to Address Compatibility Mode The Address Compatibility Mode bits
are stored on a per channel basis
6 7 2 SUMMARY OF THE DMA TRANSFER SIZES
Table 16 lists each of the DMA device transfer sizes The column labeled ‘‘Word Count Register’’ indicates
that the register contents represent either the number of bytes to transfer or the number of 16-bit words to
transfer The column labeled ‘‘Current Address Register Increment Decrement’’ indicates the number added
to or taken from the Current Address register after each DMA transfer cycle The Mode Register determines if
the Current Address register will be incremented or decremented
Table 16 DMA Transfer Size
DMA Device Date Size And Word Count
Word Count
Register
8-bit I O Count By Bytes
Bytes
16-bit I O Count By Words (Address Shifted)
Words
16-bit I O Count By Bytes
Bytes
32-bit I O Count By Bytes
Bytes
Current Address
Increment Decrement
1
1
2
4
6 7 3 ADDRESS SHIFTING WHEN PROGRAMMED FOR 16-BIT I O COUNT BY WORDS
To maintain compatibility with the implementation of the DMA in the PC AT which used the 82C37 the DMA
will shift the addresses when the Extended Mode register is programmed for or defaulted to transfers to from
a 16-bit device count6 7 3-by-words Note that the least significant bit of the Low Page register is dropped in
16-bit shifted mode When programming the Current Address register while the DMA channel is in this mode
the Current Address must be programmed to an even address with the address value shifted right by one bit
The address shifting is as shown in Table 17
Output
Address
A0
16 1
A 31 17
Table 17 Address Shifting in 16-Bit I O DMA Transfers
8-Bit I O
Programmed
Address
16-Bit I O
Programmed
Address (Shifted)
16-Bit I O
Programmed
Address (No Shift)
A0
A 16 1
A 31 17
‘‘0’’
A 15 0
A 31 17
A0
A 16 01
A 31 17
32-Bit I O
Programmed
Address (No Shift)
A0
A 16 01
A 31 17
NOTE
The least significant bit of the Low Register is dropped in 16-bit shifted mode
6 7 4 STOP REGISTERS (RING BUFFER DATA STRUCTURE)
To support a common data communication data structure (the ring buffer) a set of DMA registers have been
provided These registers are called Stop registers Each channel has 22-bits of register location associated
with it The 22-bits are distributed between three different registers (one 8-bit and two 8-bit) The Stop registers
can be enabled or disabled by writing to the channel’s corresponding Extended Mode register
The ring buffer data structure reserves a fixed portion of memory on Dword boundaries to be used for a DMA
channel Consecutively received frames or other data structures are stored sequentially within the boundaries
of the ring buffer memory
139