82374EB Datasheet, PDF (22/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Pin Name Type
Description
M16
o d MEMORY CHIP SELECT 16 M16 is an input when the ESC component owns the
ISA bus M16 is an output when an external ISA bus Master owns the ISA bus The
ISA slave memory drives this signal Low if it is a 16-bit memory device For ISA to EISA
translation cycles the ESC combinatorially asserts M16 if either EX32 or EX16
are asserted This signal has an external pull-up resistor
IO16
o d 16 BIT I O CHIP SELECT IO16 signal is used to indicate a 16-bit I O bus cycle This
signal is asserted by the I O devices to indicate that they support 16-bit I O bus cycles
All I O accesses to the ESC registers are run as 8-bit I O bus cycles This signal has
an external pull-up resistor
MRDC
t s MEMORY READ MRDC signal indicates a read cycle to the ISA memory devices
MRDC is the command to a memory slave that it may drive data onto the ISA data
bus MRDC is an output when the ESC owns the ISA bus MRDC is an input when
an external ISA Bus master owns the ISA Bus This signal is driven by the ESC during
refresh cycles
MWTC
t s MEMORY WRITE MWTC signal indicates a write cycle to the ISA memory devices
MWTC is the command to a memory slave that it may latch data from the ISA data
bus MWTC is an output when the ESC owns the ISA bus MWTC is an input when
an ISA Bus master owns the ISA Bus
SMRDC
out SYSTEM MEMORY READ SMRDC signal is asserted by the ESC to request a
memory slave to drive data onto the data lines SMRDC indicates that the memory
read cycle is for an address below the 1 MByte range on the ISA bus This signal is also
asserted during refresh cycles
SMWTC
out SYSTEM MEMORY WRITE SMWTC signal is asserted by the ESC to request a
memory slave to accept data from the data lines SMWTC indicates that the memory
write cycle is for an address below the 1 MByte range
IORC
t s I O READ IORC is the command to an ISA I O slave device that it may drive data on
to the data bus (SD 15 0 ) The device must hold the data valid until after IORC is
negated IORC is an output when the ESC component owns the ISA bus IORC is
an input when an ISA Bus master owns the ISA Bus
IOWC
t s I O WRITE IOWC is the command to an ISA I O slave device that it may latch data
from the ISA data bus (SD 15 0 ) IOWC is an output when the ESC component owns
the ISA Bus IOWC is an input when an ISA Bus master owns the ISA Bus
CHRDY
o d I O CHANNEL READY CHRDY when asserted allows ISA Bus resources request
additional time (wait-states) to complete the cycle CHRDY is an input when the ESC
owns the ISA Bus CHRDY is an input to the ESC during compatible DMA cycles
CHRDY is an output during ISA Bus master cycles to PCI slave or ESC internal register
The ESC will ignores CHRDY for ISA-Bus master accessing an ISA-Bus slave
IOCHK
in I O CHANNEL CHECK IOCHK can be asserted by any resource on the ISA Bus
When asserted it indicates that a parity or an uncorrectable error has occurred for a
device or memory on the ISA Bus A NMI will be generated to the CPU if enabled
22