82374EB Datasheet, PDF (46/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
3 1 15 GPCSM 2 0 GENERAL PURPOSE CHIP SELECT MASK REGISTER
Address Offset
Default Value
Attribute
Size
66h 6Ah 6Eh
00h
Read Write
8 Bits
This register contains the mask bits for determining the address range for which the GPCSx signals are
generated If a register bit is set to a 1 then the corresponding bit in the GPCSL register is not compared with
the address signal in the generation of the GPCSx signals If Mode Select Register (offset 40h) bit 4^e1
offset register 6Eh is ignored
Bit
Description
7 0 GPCS Mask Register The contents of these bits are used to determine which bits to compare
GPCSLA 2 0 with the address lines LA 7 0 A 1 bit means the bit should not be compared
3 1 16 GPXBC GENERAL PURPOSE PERIPHERAL X-BUS CONTROL REGISTER
Address Offset
Default Value
Attribute
Size
6Fh
xxxx x000b
Read Write
8 Bits
The register controls the generation of the X-BUS buffer output enable (XBUSOE ) signal for I O accesses to
the peripherals mapped in the General Purpose Chip Select address decode range This register determines if
the General Purpose Peripheral is placed on the XBUS or not If the General Purpose Peripheral is on the
X-Bus then the corresponding bit is set to 1 Otherwise the bit is set to 0
Bit
Description
7 3 Reserved
2 XBUSOE Generation for GPCS2 When this bit is enabled XBUSOE will be generated when
GPCS2 is generated 1^eEnabled 0^eDisabled
1 XBUSOE Generation for GPCS1 When this bit is enabled XBUSOE will be generated when
GPCS1 is generated 1^eEnabled 0^eDisabled
0 XBUSOE Generation for GPCS0 When this bit is enabled XBUSOE will be generated when
GPCS0 is generated 1^eEnabled 0^eDisabled
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