82374EB Datasheet, PDF (129/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Figure 9 Internal DMA Controller
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Each DMA channel can be programmed for 8- or 16-bit DMA device size Each channel can also be pro-
grammed for compatibility Type ‘‘A’’ Type ‘‘B’’ or Type ‘‘C’’(burst transfer) timings Each DMA channel
defaults to the PC-AT compatible settings for DMA device size channels 3 0 default to 8-bit count-by-bytes
transfers while channels 7 5 default to 16-bit count-by-words (address shifted) transfers The ESC provides
the timing control and data size translation necessary for DMA transfers between EISA ISA agents of mis-
matched bus sizes
The DMA Controller supports full 32-bit addressing Each channel includes a 16-bit ISA compatible Current
register which holds the 16 least-significant bits of the 32-bit address and an ISA compatible Low Page
register which contains the eight second most significant bits An additional High Page register contains the
eight most significant bits of the 32-bit address The address counter can be programmed as either 16-bit
compatible address counter or a full 32-bit address counter
The channels can also be programmed for any of four transfer modes The transfer modes include single
block demand or cascade Each of the three active transfer modes (single block and demand) can perform
three different types of transfers (read write or verify)
The DMA Controller also features refresh address generation and auto-initialization following a DMA termina-
tion EISA compatible buffer chaining is included as well as Stop registers to support ring buffer structures
Scatter-Gather reduces CPU overhead by eliminating reprogramming of the DMA and I O between buffers as
well as reducing the number of interrupts
The DMA Controller includes the EISA Bus arbiter which works with the PCEB’s PCI bus arbiter The arbiter
determines which requester from among the requesting DMA slaves EISA bus masters the PCI bus or
Refresh should have the bus
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