82374EB Datasheet, PDF (148/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Timer 1 Counter 1 Refresh Request Signal
This counter provides the Refresh Request signal and is typically programmed for Mode 2 operation The
counter negates Refresh Request for one counter period (833 ns) during each count cycle The initial count
value is loaded one counter period after being written to the counter I O address The counter initially asserts
Refresh Request and negates it for 1 counter period when the count value reaches 1 The counter then
asserts Refresh Request and continues counting from the initial count value
Timer 1 Counter 2 Speaker Tone
This counter provides the speaker tone and is typically programmed for Mode 3 operation The counter
provides a speaker frequency equal to the counter clock frequency (1 193 MHz) divided by the initial count
value The speaker must be enabled by a write to port 061h (see Section 3 7 on the NMI Status and Control
Ports)
Timer 2 Counter 0 Fail-Safe Timer
This counter functions as a fail-save timer by preventing the system from locking up This counter generates
an interrupt on the NMI line as the count expires by setting bit 7 on Port 0461h Software routines can avoid
the Fail-Safe NMI by resetting the counter before the timer count expires
Timer 2 Counter 2 CPU Speed Control
This counter generates the SLOWH to the CPU and is typically programmed for Mode 1 operation The
counter is triggered by the refresh request signal generated by Timer 1-Counter 1 only If the counter is
programmed the counters SLOWH output will stop the CPU for the programmed period of the one-shot
every time a refresh request occurs This counter is not configured or programmed until a speed reduction in
the system is required
8 2 Programming The Interval Timer
The counter timers are programmed by I O accesses and are addressed as though they are contained in two
separate 82C54 interval timers Timer 1 contains three counters and Timer 2 contains two counters Each
Timer is controlled by a separate Control Word register Table 22 lists the six operating modes for the interval
counters Note that for the fail safe timer (timer 2 counter 0) only mode 0 is supported
The interval timer is an I O-mapped device Several commands are available
1 The Control Word Command specifies
which counter to read or write
the operating mode
the count format (binary or BCD)
2 The Counter Latch Command latches the current count so that it can be read by the system The count-
down process continues
3 The Read Back Command reads the count value programmed mode the current state of the OUT pins
and the state of the Null Count Flag of the selected counter
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