82374EB Datasheet, PDF (37/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Pin Name
Description
4
General Purpose Chip Selects This bit is used to select the functionality of the GPCS 2 0
ECS 2 0 pins If the bit is set to 0 the GPCS 2 0 functionality is selected If the bit is set to 1
the ESC 2 0 functionality is selected
3
System Error This bit is used to disable (0) or enable (1) the generation of NMI based on
SERR signal pulsing active When this bit ^e1 (and NMIs are enabled via the NMIERTC
Register) and SERR is asserted the NMI signal is asserted When this bit ^e 0 the NMI signal
is negated and SERR is disabled from generating an NMI Note that other NMI sources are
enabled disabled via the NMISC Register
20
PIRQx Mux Mapping Control These bits select muxing mapping of PIRQ 3 0 with
MREQ 7 4 and group of X-Bus signals (DLIGHT RTCWR RTCRD ) Different bit
combinations select the number of EISA slots or group of X-Bus signals which can be
supported with the certain number of PIRQx signals by determining the functionality of pins
AEN 4 1 EAEN 4 1 MACK 3 0 EMACK 3 0 MREQ 7 4 PIRQ 3 0 DLIGHT
PIRQ0 FDCCS PIRQ1 RTCWR PIRQ2 RTCRD PIRQ3 as shown in Table 1
Bits
20
000
001
010
011
100
101
AEN 4 1
EAEN 4 1
EAEN 4 1
EAEN 4 1
EAEN 4 1
EAEN 4 1
AEN 4 1
EAEN 4 1
110 EAEN 4 1
111 EAEN 4 1
MACK 3 0
EMACK 3 0
EMACK 3 0
EMACK 3 0
EMACK 3 0
EMACK 3 0
MACK 3 0
EMACK 3 0
EMACK 3 0
EMACK 3 0
Table 1 Mode Select Register
Signal Function
MREQ 7 4
PIRQ 0 3
DLIGHT
PIRQ0
FDDCS
PIRQ1
MREQ 7 4 PIRQ0
PIRQ1
MREQ 7 4 PIRQ0
PIRQ1
MREQ 7 4 PIRQ0
FDDCS
MREQ 7 4 DLIGHT FDDCS
PIRQ 0 3
DLIGHT FDDCS
PIRQ0
PIRQ1
MREQ5
MREQ4
DLIGHT FDDCS
PIRQ0
MREQ6
MREQ5
MREQ4
DLIGHT FDDCS
MREQ 7 4 DLIGHT FDDCS
RTCWR
PIRQ2
PIRQ2
RTCWR
RTCWR
RTCWR
RTCWR
RTCWR
RTCWR
RTCWR
RTCRD
PIRQ3
PIRQ3
RTCRD
RTCRD
RTCRD
RTCRD
RTCRD
RTCRD
RTCRD
37