82374EB Datasheet, PDF (57/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Bit
Description
3 2 Addressing Mode The ESC supports 8- 16- and 32-bit DMA device data sizes The four data size
options are programmable with bits 3 2 Both the 8 bit I O ‘‘Count By Bytes’’ Mode and the 16-bit
I O ‘‘Count By Words’’ (Address Shifted) Mode are ISA compatible The 16-bit and 32-bit I O ‘‘Count
By Bytes’’ Modes are EISA extensions Byte assembly disassembly is performed by the EISA Bus
Controller Each of the data transfer size modes is discussed below
00
8-Bit I O ‘‘Count By Bytes’’ Mode
In 8 bit I O ‘‘count by bytes’’ mode the address counter can be programmed to any address The
count register is programmed with the ‘‘number of bytes minus 1’’ to transfer
01
16-Bit I O ‘‘Count By Words’’ (Address Shifted) Mode
In ‘‘count by words’’ mode (address shifted) the address counter can be programmed to any even
address but must be programmed with the address value shifted right by one bit The Page registers
are not shifted during DMA transfers Thus the least significant bit of the Low Page register is ignored
when the address is driven out onto the bus The Word Count register is programmed with the number
of words minus 1 to be transferred
10
32-Bit I O ‘‘Count By Bytes’’ Mode
In 32-bit ‘‘count by bytes’’ mode the address counter can be programmed to any byte address For
most DMA devices however it should only be programmed to a Dword aligned address If the starting
address is not Dword aligned then the DMA controller will do a partial Dword transfer during the first
and last during the first and last transfers if necessary The bus controller logic will do the byte word
assembly necessary to read or write any size memory device and both the DMA and bus controllers
support burst for this mode In this mode the Address register is usually incremented or decremented
by four and the byte count is usually decremented by four The Count register should be programmed
with the number of bytes to be transferred minus 1
11
16-Bit I O ‘‘Count By Bytes’’ Mode
In 16-bit ‘‘count by bytes’’ mode the address counter can be programmed to any byte address For
most DMA devices however it should be programmed only to even addresses If the address is
programmed to an odd address then the DMA controller will do a partial word transfer during the first
and last transfer if necessary The bus controller will do the byte word assembly necessary to write
any size memory device In this mode the Address register is incremented or decremented by two and
the byte count is decremented by the number of bytes transferred during each bus cycle The Word
Count register is programmed with the ‘‘number of bytes minus 1’’ to be transferred This mode is
offered as an extension of the two ISA compatible modes discussed above This mode should only be
programmed for 16 bit ISA DMA slaves
1 0 DMA Channel Select Bits 1 0 select the particular channel that will have its DMA Channel Extend
Mode Register programmed with bits 7 2
Bits 1 0
00
01
10
11
Channel
Channel 0 (4)
Channel 1 (5)
Channel 2 (6)
Channel 3 (7)
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