82374EB Datasheet, PDF (119/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Figure 5 Burst EISA Master to EISA Slave Cycle
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5 3 2 EISA MASTER TO 16-BIT ISA SLAVE
An ISA slave after decoding it’s address asserts M16 or IO16 The ESC monitors the EX32 EX16
M16 and IO16 signals to determine the slave type If EX32 and EX16 are negated and M16 or
IO16 is asserted the ESC performs ISA translation cycles for the EISA Bus master by generating BALE
MRDC MWRC IORC IOWC signals as appropriate The ISA slave can add wait states by negating
CHRDY The ESC samples CHRDY and translate it into EXRDY
5 3 3 EISA MASTER TO 8-BIT EISA ISA SLAVES
An 8-bit slave does not positively acknowledge it’s selection by asserting any signal The absence of an
asserted EX32 EX16 M16 and IO16 indicate to the ESC that an 8-bit device has been selected The
EISA master is backed-off the bus and the ESC takes over mastership of the EISA ISA bus The ESC will run
8-bit translation cycles on the bus by deriving the EISA control signals and the ISA control signals A slave can
extend the cycles by negating EXRDY or CHRDY signals
The ESC (Internal Registers) is accessed as an 8-bit slave
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