82374EB Datasheet, PDF (137/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
To initiate a typical Scatter-Gather transfer between memory and an I O device the following steps are
involved
1 Software prepares a Scatter-Gather Descriptor (SGD) table in system memory Each Scatter-Gather de-
scriptor is 8 bytes long and consists of an address pointer to the starting address and the transfer count of
the memory buffer to be transferred In any given SGD table two consecutive SGDs are offset by 8 bytes
and are aligned on a 4-byte boundary
2 Each Scatter-Gather Descriptor for the linked list must contain the following information
a Memory Address (buffer start) 4 bytes
b Byte Count (buffer size)
3 bytes
c End of Link List
1 bit (MSB)
Figure 15 Scatter-Gather Descriptor Format
290476 – 78
3 Initialize DMA Mode and Extended Mode registers with transfer specific information like 8- 16-bit I O
device Transfer Mode Transfer Type etc
4 Software provides the starting address of the Scatter-Gather Descriptor Table by loading the Scatter-Gather
Descriptor Table Pointer register
5 Engage the Scatter-Gather machine by writing a Start command to the Scatter-Gather Command register
6 The Mask register should be cleared as last the last step of programming the DMA register set This is to
prevent DMA from starting a transfer with a partially loaded command description
7 Once the register set is loaded and the channel is unmasked the DMA will generate an internal request to
fetch the first buffer from the Scatter Gather Descriptor Table
8 The DMA will then respond to DREQ or software requests The first transfer from the first buffer will move
the memory address and word count from the Base register set to the Current register set As long as
Scatter-Gather is active and the Base register set is not loaded and the last buffer has not been fetched the
channel will generate a request to fetch a reserve buffer into the Base register set The reserve buffer is
loaded to minimize latency problems going from one buffer to another Fetching a reserve buffer has a lower
priority than completing DMA for the channel
9 The DMA controller will terminate a Scatter-Gather cycle by detecting an End of List (EOL) bit in the SGD
After the EOL bit is detected the channel will transfer the buffers in the Base and Current register sets if
they are loaded At Terminal Count the channel will assert EOP or IRQ13 depending on its programming
and set the Terminate bit in the Scatter-Gather Status register The Active bit in the Scatter-Gather Status
register will be reset and the channel’s Mask bit will be set
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