82374EB Datasheet, PDF (13/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
PCI Bus
The PCI Bus has been defined to address the growing industry needs for a standardized local bus that is not
directly dependent on the speed and the size of the processor bus New generations of personal computer
system software such as Windows^TM and Win-NT^TM with sophisticated graphical interfaces multi-tasking and
multi-threading bring new requirements that traditional PC I O architectures can not satisfy In addition to the
higher bandwidth reliability and robustness of the I O subsystem is becoming increasingly important The PCI
environment addresses these needs and provides an upgrade path for the future PCI features include
 Processor independent
 Multiplexed burst mode operation
 Synchronous at frequencies from 20–33 MHz
 120 MByte sec usable throughput (132 MByte sec peak) for 32 bit data path
 240 MByte sec usable throughput (264 MByte sec peak) for 64 bit data path
 Optional 64 bit data path with operations that are transparent with the 32 bit data path
 Low latency random access (60 ns write access latency to slave registers from a master parked on the bus)
 Capable of full concurrency with processor memory subsystem
 Full multi-master capability allowing any PCI master peer-to-peer access to any PCI slave
 Hidden (overlapped) central arbitration
 Low pin count for cost effective component packaging (address data multiplexed)
 Address and data parity
 Three physical address spaces memory I O and configuration
 Comprehensive support for autoconfiguration through a defined set of standard configuration functions
System partitioning shown in Figure 1 illustrates how the PCI can be used as a common interface between
different portions of a system platform that are typically supplied by the chip set vendor These portions are the
Host PCI Bridge (including a main memory DRAM controller and an optional second level cache controller)
and the PCI-EISA Bridge Thus the PCI allows a system I O core design to be decoupled from the processor
memory treadmill enabling the I O core to provide maximum benefit over multiple generations of processor
memory technology For this reason the PCI-EISA Bridge can be used with different processors Regardless
of the new requirements imposed on the processor side of the Host PCI Bridge (e g 64-bit data path 3 3V
interface etc ) the PCI side remains unchanged which allows reusability not only of the rest of the platform
chip set (i e PCI-EISA Bridge) but also of all other I O functions interfaced at the PCI level These functions
typically include graphics SCSI and LAN
EISA Bus
The EISA bus in the system shown in the Figure 1 0 represents a second level I O bus It allows personal
computer platforms built around the PCI as a primary I O bus to leverage the large EISA ISA product base
Combinations of PCI and EISA buses both of which can be used to provide expansion functions will satisfy
even the most demanding applications
Along with compatibility with 16-bit and 8-bit ISA hardware and software the EISA bus provides the following
key features
 32-bit addressing and 32-bit data path
 33 MByte sec bus bandwidth
 Multiple bus master support through efficient arbitration
 Support for autoconfiguration
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