82374EB Datasheet, PDF (124/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Cycle Type
Memory
Read Write
Memory
Read Write
I O Read Write
I O Read Write
DMA Compatible
DMA Type A⁽¹⁾
DMA Type B⁽¹⁾
DMA Type C⁽²⁾
Table 10 Number of BCLKs for ISA Master Cycles
Bus
Size
No Wait State
NOWS ^e0
Standard CHRDY^e1
NOWS ^e1
Number of BCLKs
16
2
3
8
45
6
16
3
3
8
45
6
8 16
8
8
8 16
NA
6
8 16
NA
4
8 16
NA
2
NOTES
1 If ISA memory responds the ESC will extend the cycle by 1 BCLK
2 If ISA memory responds the ESC will use DMA Type B read cycle timing
One Wait State
CHRDY^e0
4
7
4
7
10
7
5
3
5 5 Mis-Match Cycles
Data size translation is performed by the ESC for all mis-matched cycles A mis-matched cycle is defined as a
cycle in which the bus master and bus slave do not have equal data bus sizes (e g a 32-bit EISA master
accessing a 16-bit ISA slave) The data size translation is performed in conjunction with the PCEB The ESC
generates the appropriate cycles and data steering control signals for mis-matched cycles The PCEB uses
the data steering control signals from the ESC to latch and redirect the data to the appropriate byte lanes The
ESC will perform one or more of the following operations depending on the master and slave type transfer
direction and the number of byte enables active
Master Type
32-bit EISA with 16-bit
downshift
32-bit EISA
16-bit EISA
Table 11 Mis-Match Master Slave Combinations
Cycle Type
Slave Type
32-Bit
EISA
16-Bit
EISA
16-Bit
ISA
Standard
Burst
match
match
Mis-Match
match
Mis-Match
na
Standard
Burst
match
match
Mis-Match
na
Mis-Match
na
Standard
Burst
Mis-Match
Mis-Match
match
match
Mis-Match
na
8-Bit
EISA ISA
Mis-Match
na
Mis-Match
na
Mis-Match
na
NOTE
na Not Applicable The cycle will never occur
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