82374EB Datasheet, PDF (64/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
3 2 11 DMA MEMORY LOW PAGE REGISTER DMA MEMORY BASE LOW PAGE REGISTER
Register Location
Default Value
Attribute
Size
087h DMA Channel 0
083h DMA Channel 1
081h DMA Channel 2
082h DMA Channel 3
08Bh DMA Channel 5
089h DMA Channel 6
08Ah DMA Channel 7
00h
Read Write
8 Bits per channel
Each channel has an 8-bit Low Page register associated with it The DMA memory Low Page register contains
the eight second most-significant bits of the 32-bit address It works in conjunction with the DMA controller’s
High Page register and Current Address register to define the complete (32-bit) address for the DMA channel
This 8-bit register is read or written directly by the processor or bus master It may also be re-initialized by an
autoinitialize back to its original value autoinitialize takes place only after a TC or EOP
Each channel has a Base Low Page Address register located at the same port address as the corresponding
Current Low Page register These registers store the original value of their associated Current Low Page
registers During autoinitialize these values are used to restore the Current Low Page registers to their original
values The 8-bit Base Low Page registers are written simultaneously with their corresponding Current Low
Page register by the microprocessor The Base Low Page registers cannot be read by any external agents
During Scatter-Gather these registers store the 8 bits from the third byte of the current memory address
During a Scatter-Gather transfer the DMA will load a reserve buffer into the base memory address register
In Chaining Mode these register store the 8 bits from the third byte of the current memory address The CPU
will program the base register set with a reserve buffer
Bit
Description
7 0 DMA LOW PAGE AND BASE LOW PAGE These bits represent the eight second most-significant
address bits when forming the full 32-bit address for a DMA transfer Upon reset or Master Clear the
value of these bits is 00h
3 2 12 DMAP DMA PAGE REGISTER
Register Location
Default Value
Attribute
Size
080h 84h 85h 86h 88h 8Ch 8Dh 8Eh
xxh
Read Write
8 Bits
These registers have no effect on the DMA operation These registers provide extra storage space in the I O
space for DMA routines
Bit
Description
7 0 DMA PAGE These bit have no effect on the DMA operation These bits only provide storage space in
the I O map
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