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82374EB Datasheet, PDF (45/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)
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82374EB 82374SB
Bit
Description
7 Routing of Interrupts When enabled (0) this bit routes the PCI Interrupt signal to the PC compatible
interrupt signal specified in bits 6 0 After a reset or a power-on this bit is disabled (set to 1)
6 0 IRQx Routing Bits These bits specify which IRQ signal to generate when the PCI Interrupt for this
register has been triggered
Bits 6 0
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
IRQx
Reserved
Reserved
Reserved
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Reserved
Bits 6 0
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000 to
1111111
IRQx
IRQ9
IRQ10
IRQ11
IRQ12
Reserved
IRQ14
IRQ15
Reserved
3 1 13 GPCSLA 2 0 GENERAL PURPOSE CHIP SELECT LOW ADDRESS REGISTER
Address Offset
Default Value
Attribute
Size
64h 68h 6Ch
00h
Read Write
8 Bits
This register contains the low byte of the General Purpose Peripheral mapping address The contents of this
register are compared with the LA 7 0 address lines The contents of this register the GPCSHA Register and
the GPCSM Register control the generation the GPCS 2 0 signal or the ESC 2 0 signal (101 110 combina-
tion) If Mode Select Register (offset 40h) bit 4e1 offset register 6Ch is ignored
Bit
Description
7 0 GPCS Low Address Byte The contents of these bits are compared with the address lines LA 7 0 to
generate the GPCS 2 0 signal or the ECS 2 0 combination for this register The mask register
(GPCSM 2 0 ) determines which bits to use during the comparison
3 1 14 GPCSHA 2 0 GENERAL PURPOSE CHIP SELECT HIGH ADDRESS REGISTER
Address Offset
Default Value
Attribute
Size
65h 69h 6Dh
C0h
Read Write
8 Bits
This register contains the high byte of the General Purpose Peripheral mapping address The contents of this
register are compared with the LA 15 8 address lines The contents of this register the GPCSLA Register and
the GPCSM Register control the generation the GPCS 2 0 signal or the ESC 2 0 signal (101 110 combina-
tion) If Mode Select Register (offset 40h) bit 4e1 offset register 6Dh is ignored
Bit
Description
7 0 GPCS High Address Byte The contents of these bits are compared with the address lines LA 15 8
to generate the GPCS 2 0 signal or the ECS 2 0 combination for this register
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