82374EB Datasheet, PDF (154/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Note that externally the interrupt acknowledge cycle sequence appears different than in a traditional discrete
82C59 implementation However the traditional interrupt acknowledge sequence is generated within the ESC
and it is an EISA compatible implementation
1 One or more of the Interrupt Request (IRQ x ) lines are raised high setting the corresponding IRR bit(s)
2 The Interrupt Controller evaluates these requests and sends an INTR to the CPU if appropriate
3 The CPU acknowledges the INTR and responds with an interrupt acknowledge cycle This cycle is translat-
ed into a PCI bus command This PCI command is broadcast over the PCI bus as a single cycle as opposed
to the two cycle method typically used
4 Upon receiving an interrupt acknowledge cycle from the CPU over the PCI the PCEB converts the single
cycle into an INTA pulse to the ESC The ESC uses the INTA pulse to generate the two cycles that the
internal 8259 pair can respond to with the expected interrupt vector The cycle conversion is performed by a
functional block in the ESC Interrupt Controller Unit The internally generated interrupt acknowledge cycle is
completed as soon as possible as the PCI bus is held in wait states until the interrupt vector data is
returned Each cycle appears as an interrupt acknowledge pulse on the INTA pin of the cascaded inter-
rupt controllers These two pulses are not observable at the ESC periphery
5 Upon receiving the first internally generated interrupt acknowledge the highest priority ISR bit is set and the
corresponding IRR bit is reset The Interrupt Controller does not drive the Data Bus during this cycle On the
trailing edge of the first cycle pulse a slave identification code is broadcast by the master to the slave on a
private internal three bit wide bus The slave controller uses these bits to determine if it must respond with
an interrupt vector during the second INTA cycle
6 Upon receiving the second internally generated interrupt acknowledge the Interrupt Controller releases an
8-bit pointer (the interrupt vector) onto the Data Bus where it is read by the CPU
7 This completes the interrupt cycle In the AEOI mode the ISR bit is reset at the end of the second interrupt
acknowledge cycle pulse Otherwise the ISR bit remains set until an appropriate EOI command is issued at
the end of the interrupt subroutine
If no interrupt request is present at step four of either sequence (i e the request was too short in duration) the
Interrupt Controller will issue an interrupt level 7
9 3 80x86 Mode
When initializing the control registers of the 82C59 an option exists in Initialization Control Word Four (ICW4)
to select either an 80x86 or an MSC-85 microprocessor based system The interrupt acknowledge cycle is
different in an MSC-85 based system than in the 80x86 based system the interrupt acknowledge takes three
INTA pulses with the MSC-85 rather than the two pulses with the 80x86 The ESC is used only in an 80x86
based system You must program each interrupt controller’s ICW4 bit 0 to a ‘‘1’’ to indicate that the interrupt
controller is operating in an 80x86 based system This setting ensures proper operation during an interrupt
acknowledge
9 3 1 ESC INTERRUPT ACKNOWLEDGE CYCLE
As discussed the CPU generates an interrupt acknowledge cycle that is translated into a single PCI command
and broadcast across the PCI bus to the PCEB The PCEB pulses the INTA signal to the ESC The ESC
Interrupt Unit translates the INTA signal into the two INTA pulses expected by the interrupt controller
subsystem The Interrupt Controller uses the first interrupt acknowledge cycle to internally freeze the state of
the interrupts for priority resolution The first controller (CNTRL-1) as a master issues a three bit interrupt
code on the cascade lines to CNTRL-2 (internal to the ESC) at the end of the INTA pulse On this first cycle
the interrupt controller block does not issue any data to the processor and leaves its data bus buffers disabled
CNTRL-2 decodes the information on the cascade lines compares the code to the byte stored in Initialization
154