82374EB Datasheet, PDF (143/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
Upon the expiration of a Current Buffer the new Base register contents should be programmed and both the
Chaining Mode Enabled and Program complete bits of the Chaining Mode register should be set This resets
the interrupt if the CPU was the programming master and allows for the next Base register to Current register
transfer If the Program Complete bit is not set before the current transfer reaches TC then the DMA controller
will set the Mask bit and the TC bit in the Status register and stop transferring data In this case an over-run is
likely to occur To determine if this has a read of either Status register or the Mask register can be done (the
Mask register has been made readable) If the channel is masked or has registered a TC the DMA channel
has been stopped and the full address count and chaining mode must be programmed to return to normal
operation
Note that if the CPU is the programming master an interrupt will only be generated if a Current Buffer expires
and chaining mode is enabled It will not occur during initial programming The Channel Interrupt Status
register will indicate pending interrupts only That is it will indicate an empty Base register with Chaining Mode
enabled When Chaining mode is enabled only the Base registers are written by the processor and only the
Current registers can be read The Current registers are only updated on a TC
6 11 Refresh Unit
The ESC provides an EISA Bus compatible refresh unit that provides 14 bits of refresh address for EISA ISA
bus DRAMs that do not have their own local refresh units The refresh system uses the combined functions of
the Interval Timers the DMA Arbiter DMA address counter and EISA Bus Controller Functionally the Re-
fresh unit is a sub-section of the ESC DMA unit The DMA Address Counter is used to increment the Refresh
Address register following each refresh cycle Interval Counter 1 Timer 1 generates an internal refresh re-
quest The DMA Arbiter detects a Refresh signal from either the Counter Timer or the REFRESH input and
determines when the refresh will be done The DMA drives the refresh address out onto the LA address bus
The cycle is decoded and driven onto the EISA address bus by the EISA Bus Controller The ESC EISA Bus
Controller is responsible for generating the EISA cycle control signals Timer 1 Counter 1 should be pro-
grammed to provide a refresh request about every 15 ms
Requests for refresh cycles are generated by two sources the ESC (Timer 1 Counter 1) and 16-bit masters
that activate REFRESH when they own the EISA bus
If a 16-bit ISA bus master holds the bus longer than 15 ms it must initiate memory refresh cycles If the ISA
Master initiates a Refresh cycle while it owns the bus it floats the address lines and cycle control signals and
asserts REFRESH to the ESC The ESC EISA Bus Controller generates the cycle control signals and the
ESC DMA Refresh unit supplies the refresh address The ISA Master must then wait one BCLK after MRDC
is negated before floating REFRESH and driving the address lines and control signals
Typically the refresh cycle length is five BCLK’s The I O slave can insert one wait state to extend the cycle to
six BCLK’s by asserting CHRDY The ESC EISA Bus Controller upon seeing REFRESH knows to run
refresh cycles instead of DMA cycles
7 0 EISA BUS ARBITRATION
The ESC receives requests for EISA Bus ownership from several different sources from DMA devices from
the Refresh counter from EISA masters and from PCI agents PCI agents requesting the EISA Bus request the
EISA Bus through the PCEB Additionally 16-bit ISA Masters may request the bus through a cascaded DMA
channel (see the Cascade mode description in Section 6 2 4)
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