82374EB Datasheet, PDF (166/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
10 0 ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
In addition to the standard EISA compatible interrupt controller described in the previous section the ESC
incorporates the Advanced Programmable Interrupt Controller (APIC) While the standard interrupt controller is
intended for use in a uni-processor system APIC can be used in either a uni-processor or multi-processor
system APIC provides multi-processor interrupt management and incorporates both static and dynamic sym-
metric interrupt distribution across all processors In systems with multiple I O subsystems each subsystem
can have its own set of interrupts
In a uni-processor system APIC’s dedicated interrupt bus can reduce interrupt latency over the standard
interrupt controller (i e the latency associated with the propagation of the interrupt acknowledge cycle across
multiple busses using the standard interrupt controller approach) Interrupts can be controlled by the standard
EISA compatible interrupt controller unit the I O APIC unit or mixed mode where both the standard and I O
APIC are used The selection of which controller responds to an interrupt is determined by how the interrupt
controllers are programmed Note that it is the programmer’s responsibility to make sure that the same
interrupt input signal is not handled by both interrupt controllers
At the system level APIC consists of two parts (Figure 23) one residing in the I O subsystem (called the I O
APIC) and the other in the CPU (called the Local APIC) The ESC contains an I O APIC unit The local APIC
and the I O APIC communicate over a dedicated APIC bus The ESC’s I O APIC bus interface consists of two
bi-directional data signals (APICD 1 0 ) and a clock input (APICCLK)
The CPU’s Local APIC Unit contains the necessary intelligence to determine whether or not its processor
should accept interrupts broadcast on the APIC bus The Local Unit also provides local pending of interrupts
nesting and masking of interrupts and handles all interactions with its local processor (e g the INTR INTA
EOI protocol) The Local Unit further provides inter-processor interrupts and a timer to its local processor The
register level interface of a processor to its local APIC is identical for every processor
Figure 23 APIC System Structure
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