82374EB Datasheet, PDF (44/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
3 1 11 APICBASE APIC BASE ADDRESS RELOCATION
Address Offset
Default Value
Attribute
Size
59h
00h
Read Write
8 Bits
The APICBASE Register provides the modifier for the APIC base address
82374EB
APIC is mapped in the CPU memory space at the locations FEC0 x000h and FEC0 x010h (x^e0-Fh) The
value of ‘‘x’’ is defined by bits 5 2 Thus the relocation register provides a 4 KByte address granularity The
default value of 00h provides APIC unit mapping at the addresses FEC00000h and FEC00010h
82374SB
APIC is mapped in the CPU memory space at the locations FEC0 xy00h and FEC0 xy10h (x^e0-Fh
y^e0 4 8 Ch) The value of ‘‘y’’ is defined by bits 1 0 and value of ‘‘x’’ is defined by bits 5 2 Thus the
relocation register provides a 1 KByte address granularity (i e potentially up to 64 I O APICs can be uniformly
addresses in the memory space) The default value of 00h provides APIC unit mapping at the addresses
FEC00000h and FEC00010h
Bit
Description
7 6 Reserved
5 2 X-Base Address R W Bits 5 2 are compared to host address bits A 15 12 respectively
1 0 82374EB Reserved
82374SB Y-Base Address R W Bits 1 0 are compared to host address bits A 11 10
respectively
3 1 12 PIRQ 0 3 PIRQ ROUTE CONTROL REGISTERS
Address Offset
Default Value
Attribute
Size
60h 61h 62h 63h
80h
Read Write
8 Bits
These registers control the routing of PCI Interrupts (PIRQ 0 3 ) to the PC compatible interrupts Each PCI
interrupt can be independently routed to 1 of 11 compatible interrupts
Interrupt Steering Programming Considerations
When using the PCI programmable interrupt steering feature the following programming considerations apply
1 Any interrupt steered to by a PIRQx must be programmed to level sensitive mode
2 For an interrupt used as a PIRQx that IRQ pin is also level sensitive It is not permissible to use an
interrupt on the EISA ISA Bus as edge triggered as well as on the PCI Bus as level sensitive
3 Registers that must be programmed when using a PIRQx include the Mode Select Registers Edge Level
Registers PIRQ 3 0 Route Control Registers and the Interrupt Mask Registers (listed in suggested
programming order)
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