82374EB Datasheet, PDF (71/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
3 2 22 SCAGAST SCATTER-GATHER STATUS REGISTER
Register Location
Default Value
Attribute
Size
Channels 0
0419h Channels 1
041Ah Channels 2
041Bh Channels 3
041Dh Channels 5
041Eh Channels 6
041Fh Channels 7
08h
Read Only Relocatable
8 Bits
The Scatter-Gather Status Register provides Scatter-Gather process status information to the CPU or Master
An active bit is set to 1 after the S-G Start command is issued The active bit will be 0 before the initial start
command following a terminal count and after an S-G Stop command is issued The Current Buffer and Base
Buffer State Bits indicate whether the corresponding register has a buffer loaded It is possible for the Base
Buffer State to be set while the Current Buffer State is cleared When the Current Buffer transfer is complete
the Base Buffer will not be moved into the Current Buffer until the start of the next data transfer Thus the
Current Buffer State is empty (cleared) while the Base Buffer State is full (set) The Terminate bit is set active
after a Stop command after TC for the last buffer in the list and both Base and Current buffers have expired
The EOP and IRQ13 Bits indicate which end of process indicator will be used to alert the system of an S-G
process termination The EOL status bit is set if DMA controller has loaded the last buffer of the Link List
Bit
Description
7 Next Link Null Indicator If the Next SGD fetched from memory during a fetch operation has the EOL
value (1) the current value of the Next Link register is not overwritten Instead bit 7 of the channel’s
S-G Status register the Next Link Null indicator is set to a 1 If the fetch returns a EOL value not equal
to (1) this bit is reset to 0 This status bit is written after every fetch operation Following reset or
Master Clear this bit is reset to 0 This bit is also cleared by an S-G Start Command Write
6 Reserved
5 IRQ13 or EOP on Last Buffer When the IRQ13 EOP status bit is 1 EOP was either defaulted to at
reset or selected through the S-G Command register as the S-G process termination indicator EOP
will be issued to alert the system when a terminal count occurs or following the Stop Command When
this bit is returned as a 0 an IRQ13 will be issued to alert the CPU of this same status
4 Reserved
3 S-G Base Buffer State When the Base Buffer status bit contains a 0 the Base Buffer is empty When
the Base Buffer Status bit is set to 1 the Base buffer has a buffer link loaded Note that the Base
Buffer State may be set while the Current buffer state is cleared This condition occurs when the
Current Buffer expires following a transfer the Base Buffer will not be moved into the Current Register
until the start of the next DMA transfer
2 S-G Current Buffer State When the Current Buffer status bit contains a 0 the Current Buffer is
empty When the Current Buffer status bit is set to 1 the Current Buffer has a buffer link loaded and is
considered full Following reset bit 2 is reset to 0
1 Reserved
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