82374EB Datasheet, PDF (126/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
RE-DRIVE
This occurs during reads and writes when both the master and slave are on the EISA ISA bus and the PCEB is
neither a master nor a slave The re-drive function is always performed in conjunction with assembly disas-
sembly During the assembly process the last cycle is a re-drive cycle During disassembly all the cycles
except the first cycle are re-drive cycles
5 7 Servicing DMA Cycles
The ESC is responsible for performing DMA transfers If the memory is determined (EX32 or EX16 assert-
ed) to be on the EISA bus the DMA cycle can be ‘‘A’’ ‘‘B’’ or ‘‘C’’ type If the memory is determined to be on
the ISA bus then the DMA cycle will run as a compatible cycle The DMA transfers are described in detail in
Section 8 0
5 8 Refresh Cycles
The ESC support refresh cycles on the EISA ISA bus The ESC asserts the REFRESH signal to indicate
when a refresh cycle is in progress Refresh cycles are generated by two sources the refresh unit inside the
ESC or an external ISA bus masters The EISA bus controller will enable the address lines LA 15 2 and the
BE 3 0 The High and Low Page register contents will also be placed on the LA 31 16 bus during refresh
Memory slaves on the EISA ISA bus must not drive any data onto the data bus during the refresh cycle Slow
memory slaves on the EISA ISA may extend the refresh cycle by negating the EXRDY or CHRDY signal
respectively The refresh cycles are also described in Section 6 11
5 9 EISA Slot Support
The ESC support up of 8 EISA slots The ESC provides support for the 8 slots as follows
 The ESC address and data output buffers directly drive 240 pF capacitive load on the Bus
 The ESC generates slot specific AENx signals
 The ESC supports EISA masters in all 8 slots
The ESC generates encoded AENs and encoded Master Acknowledge signals for 8 slots and 8 masters
These signals must to decoded on the system board to generate the slot specific AENx signals and MACKx
signals The ESC can be programmed through Mode Select register bit 1 0 to directly generate these signals
for 4 slots and 4 masters
5 9 1 AEN GENERATION
The ESC directly generates the slot specific AEN signals if the ESC is configured to support 4 AENx (Table
12) If the ESC is programmed to support more than 4 EISA AENx the ESC will generate Encoded AEN
signals Discrete logic like a F138 is required to generate the slot specific AENs
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