82374EB Datasheet, PDF (27/208 Pages) Intel Corporation – SYSTEM COMPONENT (ESC)

82374EB 82374SB
2 7 Interrupt Controller Signals
Pin Name
IRQ 15 9
IRQ8
IRQ 7 3 1
INTR
NMI
Type
in
out
out
Description
INTERRUPT REQUEST IRQ These signals provide both system board components
and EISA bus I O devices with a mechanism for asynchronously interrupting the CPU
The assertion mode of each interrupt can be programmed to be edge or level
triggered An asserted IRQ input must remain asserted until after the falling edge of
INTA If the input is negated before this time a DEFAULT IRQ7 will occur when the
CPU acknowledges the interrupt
IRQ8 requires an external pull-up resistor (8 KX –10 KX)
CPU INTERRUPT INTR is driven by the ESC to signal the CPU that an Interrupt
request is pending and needs to be serviced It is asynchronous with respect to BCLK
or PCICLK and it is always an output The interrupt controllers must be programmed
following a reset to ensure that this pin takes on a known state Upon reset the state of
this pin is undefined
NON-MASKABLE INTERRUPT NMI is used to force a non-maskable interrupt to the
CPU The CPU registers an NMI when it detects a rising edge on NMI NMI will remain
active until a read from the CPU to the NMI register at port 061h is detected by the
ESC This signal is set to low upon reset
2 8 APIC Bus Signals
Pin Name
APICCLK
APICD 1 0
Type
Description
in APIC BUS CLOCK APICCLK provides the timing reference for the APIC Bus
Changes on APICD 1 0 are synchronous to the rising edge of APICCLK
od APIC DATA APICD1 and APICD0 are the APIC data bus signals Interrupt messages
are sent received over this bus APIC arbitration uses APICD1
2 9 System Power Management Signals (82374SB Only)
Pin Name
STPCLK
SMI
Type
out
out
Description
STOP CLOCK STPCLK is asserted by the ESC in response to one of many
maskable hardware or software events For 3 3V processors that are not 5V tolerant
STPCLK is driven to the CPU STPCLK pin through a 5V to 3 3V translator When
the CPU samples STPCLK asserted it responds by stopping its internal clock After a
hard reset this signal is negated
SYSTEM MANAGEMENT INTERRUPT SMI is asserted by the ESC in response to
one of many maskable hardware or software events For 3 3V processors that are not
5V tolerant SMI is driven to the CPU SMI pin through a 5V to 3 3V translator The
CPU recognizes the falling edge of SMI as the highest priority interrupt in the system
The CPU responds by entering SMM (System Management Mode) SMI is negated
during and following reset After a hard reset this signal is negated
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